Logic circuits, such as multistage parallel adder circuits used for the addition of multiple-bit binary numbers, are well known in the art. Typically, in parallel adders, all bits of two binary numbers are applied to the input terminals of the adder stages in parallel, and each stage generates a sum output signal and a carry signal. For each stage, other than the first stage, both the sum and the carry signals are functions of the values of the input bits and the carry signal received from the preceding stage. Thus, the sum output signals do not represent a steady state condition until carry propagation has been completed through all stages.
One use of the parallel adder is in the so-called synchronous mode, in which the adder sum is not used until sufficient time has elapsed to guarantee carry completion. In another mode of operation, the so-called asynchronous mode, the completion of the add operation is determined by detection of completion of carry propagations. One prior art arrangement generates not only the carry, but also the not-carry signal for each adder stage and uses carry complete logic circuitry to generate a completion signal when either a carry or not-carry signal is received for each stage. However, this prior art adder suffers from the problem of requiring complex carry complete logic circuitry, which increases in size and complexity as the number of binary number bits increases.